Generally, minterm and maxterm based canonical forms are utilized to express the logical function with all logical implicants in the 2n space, where n is the number of variables in the logical expression of the function. Primarily, minterm expressions are used on a Karnough map like environment to obtain the most simplified form of the expression with prime implicants before hardware realizations. After the most simplified logical expression, hardware implementations take place. Two analysis procedures are essential for the logical gate level realizations. The first one is the functional analysis, whereas the second one is the timing analysis. The functional analysis includes signal labeling and logical functional analysis of successive stages from input to output. After passing each gate, the logical expression containing input variables or input expressions may be very complicated to express using Boolean algebra operators. In this work, instead of this classical approach, a novel minterm dependent method is proposed. After first stage gates, all signals and inputs to the next stage are expressed with minterm and maxterm forms on the circuit schematic. Maxterm expressions are converted to minterm canonical form after each OR gate or NOR gate pass. From input to output, functional analysis is done without using any variable name or Boolean operation expression. Minterm based terms are used to obtain the final output on the circuit schematic. The proposed method is applied to different logical circuits, and the results proved the efficiency of it. The method prevents the computational error occurring probability while dealing with the complicated logical functions. A straightforward and effective analysis procedure is introduced and tested through the work.
Anahtar Kelimeler: Logical analysis, Logic circuits, Logic minimization
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